- DDR memory module: 200-pin SO-DIMM PC3200 (200/400 MHz), 512 MB.
- On-board memory: PC3200 (200/400 MHz) DDR memory, 512 MB fast SRAM, 16 M-bits.
- FPGA: Altera Stratix II EP2S130F1508 (EP2S180F1508 may available).
- Interface: USB 2.0 and PCI.
- Accverinos series functional module can be mounted (Assured 200 MHz data transfer speed between B-10 and the functional module).
- Maximum 2M ASIC gate count circuit (when using EP2S180 and M-10 functional module).
- Flexible connectivity by using PCI board or custom interface board.
- Chain connectivity with multiple B-10 Base Systems.
- Total 780 user I/O (excluding memory interfaces).
- Gated-clock can be realized on B-10 Base System.
- Micro ATX chassis (easy to use).
- Sample FPGA circuit core-IP and PC base software.
- Sample software (Windows driver and application software) supplied as source code.

· UWSCSI connectors can be freely used by users.
· Accverinos functional modules can be mounted to CN1 - CN4.
· SRAM can be used as shared memory for the Accverinos function modules.
· Commercial PCI board can be connected to the PCI connectors.
· PCI-Express connectors can be used as user I/O.
· PLL provides unskewed CLK to Stratix II, Cyclone II, Accverinos functional modules. For each CLK system, gated clocks are available.

· DDR memory controller
· High speed transmission circuit between FPGAs
· PLL control circuit